Axon Network Virtual Storage
for High Performance Distributed Applications

James P.G. Sterbenz and Gurudatta M. Parulkar,
“Axon: Network Virtual Storage Design”,
SIGCOMM Computer Communication Review, Vol.20 #2,
ACM SIGCOMM, New York, April 1990, pp. 50–65.
[ PostScript | WUCS-89-13.ps ]

ABSTRACT

This paper describes network virtual storage (NVS) in the Axon host communication architecture for distributed applications. The Axon project is investigating an integrated design of host architecture, operating systems, and communication protocols to allow applications to utilise the high bandwidth provided by the next generation of communications networks. NVS extends segmented paged virtual storage management and address translation mechanisms to include segments located across an internetwork. This provides the ability to efficiently use the shared memory paradigm in distributed systems for high performance applications such as scientific visualisation and imaging.

Keywords

High-bandwidth low-latency gigabit zero-copy host-network interface, very high-speed internet, VHSI, distributed virtual shared memory, DVSM, DSM, network virtual storage, Multics, NVS, application-oriented lightweight transport protocol, ALTP, distributed scientific visualisation

Outline

1. Introduction
2. The Axon Architecture
   1. IPC in the Axon architecture
      • Generalised remote procedure call (GRPC)
      • Segment streaming
   2. System level IPC support
   3. Transport protocol
   4. Host architecture
   5. Communications processor architecture
3. Network Virtual Storage
   1. Address translation extensions
   2. Implementation
      • Segment types
      • Host name binding
        • KST – known segment table
        • KHT – known host table
        • HAT – host address table
        • HND – host name database
      • Remote segment location
      • Performance aspects
4. Storage Management
   1. Replacement policy
   2. Remote segment placement policy
      • AS – auxiliary storage
      • RS – real storage
      • FB – frame buffer
      • RAS – real and auxiliary storage
5. Related Work
6. Conclusions

• References
• Acknowledgments
  • Work performed while James P.G. Sterbenz on leave of absence from IBM Corp., Rochester MN.
  • This work supported in part by Bellcore, BNR, Itatel SIT NEC, Southwestern Bell, and NSF grant DCI-8600947

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©2003 James P.G. Sterbenz <jpgs@sterbenz.org>